Make: Synopsys, Inc.
Model: Asia Pac Frontend University Bundle Asia Pac Backend University Bundle
- Capabilities
- Synopsys Front End Bundle includes RTL ASIC Synthesis, high level synthesis, FPGA Synthesis and Multi-FPGA partitioning, test insertion and ATPG, logic simulation, logical equivalence checking, and signoff timing analysis.
- Synopsys Back end bundle includes tools for Physical implementation, RC extraction, DRC, LVS, Signoff Rail analysis.
- Applications
ASIC Design, Analog IC Design, PCB Design, Testing and Verification.
- Location
Room No.: 237, 237A & 238
Second Floor
Technology Tower
IC Design Laboratory
School of Electronics Engineering
- Contact
Dr. Nithish Kumar,
Associate Professor Grade 2,
Department of Micro and Nano Electronics,
School of Electronics Engineering (SENSE),
VIT, Vellore, TN-632014.
Email: sense.eda2@vit.ac.in
Phone: 0416-2202490